EDN

Synopsys extends formal reach with InnoLogic acquisition

SAN MATEO, Calif. — Adding an equivalence checker for memory and full-custom designs to its verification arsenal, Synopsys Inc. announced Wednesday (June 25) that it has purchased privately held ...
EDN

Synopsys Tips ‘Hybrid’ Formal Verification

Claiming a new approach to functional RTL verification, Synopsys Inc. this week will announce a hybrid product that combines a formal property-checking capability with the company's VCS Verilog ...
Design-Reuse

Synopsys gives equivalency checker a new look

MOUNTAIN VIEW, Calif. — In an effort to make formal equivalency checking more accessible to designers who aren't formal-verification experts, Synopsys Inc. this week will roll out a "flow-based" user ...
Nasdaq

Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs

VC Formal Datapath Validation application delivers over 100X speed-up in formal verification between a reference C/C++ algorithm and RTL design implementation over conventional techniques The new app ...
Electronic Design

Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...